View NCV8675DT50RKG_8317621.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2011 august, 2011 ? rev. 7 1 publication order number: ncv8675/d ncv8675 350 ma very low i q low dropout linear regulator with reset and reset delay the ncv8675 is a precision 5.0 v and 3.3 v fixed output, low dropout integrated voltage regulator with an output current capability of 350 ma. careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent ground current of 34 a. ncv8675 is pin for pin compatible with ncv4275 and it could replace this part when very low quiescent current is required. the output voltage is accurate within 2.0% for d 2 pak ? 5 package and 2.5% for dpak ? 5 package, and maximum dropout voltage is 600 mv at full rated load current. it is internally protected against input transients, input supply reversal, output overcurrent faults, and excess die temperature. no external components are required to enable these features. features ? 5 v and 3.3 v fixed output (2.5 v version available upon request) ? 2.0% or 2.5% output accuracy, over full temperature range ? 34 a typical quiescent current at i out = 100 a, 50 a maximum up to 85 c ? 600 mv maximum dropout voltage at 350 ma load current ? wide input voltage operating range of 4.5 v to 45 v ? internal fault protection ? ? 42 v reverse voltage ? short circuit/overcurrent ? thermal overload ? aec ? q100 qualified ? emc compliant ? ncv prefix for automotive and other applications requiring site and control changes ? these are pb ? free devices figure 1. block diagram ? + bandgap reference thermal shutdown reset generator current limit and saturation sense error amplifier v in d v out gnd ro see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information marking diagrams http://onsemi.com d 2 pak ? 5 ds suffix case 936a xx = 50 (5.0 v version) = 33 (3.3 v version) a = assembly location wl, l = wafer lot y = year ww = work week g = pb ? free package nc v8675 ? xx awlywwg pin 1. v in 2. ro tab, 3. gnd* 4. d 5. v out * tab is connected to pin 3 on all packages 1 1 5 v675xxg alyww dpak ? 5 dt suffix case 175aa
ncv8675 http://onsemi.com 2 pin descriptions symbol function v in unregulated input voltage; 4.5 v to 45 v; battery input voltage. bypass to gnd with a ceramic capacitor. ro reset output; open collector active reset (accurate when v in > 1.0 v) gnd ground; pin 3 internally connected to tab d reset delay; timing capacitor to gnd for reset delay function v out output; 350 ma. 22 f, esr < 9 maximum ratings pin symbol, parameter symbol min max unit input voltage v in ? 42 45 v output voltage v out ? 0.3 16 v reset output voltage v ro ? 0.3 25 v reset output current i ro ? 5.0 5.0 ma reset delay voltage v d ? 0.3 7.0 v reset delay current i d ? 2.0 2.0 ma storage temperature t stg ? 55 +150 c esd capability ? human body model ? machine model ? ? 4 200 kv v storage temperature t stg ? 55 +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. operating range pin symbol, parameter symbol min max unit input voltage operating range v in 4.5 45 v junction temperature t j ? 40 150 c thermal resistance parameter symbol min max unit junction ambient d 2 pak r thja 82.1 c/w junction case d 2 pak r thjc 4.3 junction ambient dpak r thja 112.2 c/w junction case dpak r thjc 4.3 1. 1 oz., 100 mm 2 copper area. pb soldering temperature and msl parameter symbol min max unit lead temperature soldering reflow (smd styles only), pb ? free (note 2) t sld 265 pk c moisture sensitivity level msl 1 ? 2. pb ? free, 60 sec ? 150 sec above 217 c, 40 sec maximum at peak.
ncv8675 http://onsemi.com 3 electrical characteristics v in = 13.5 v, t j = ? 40 c to +150 c, unless otherwise specified parameter symbol test conditions min typ max unit output output voltage d 2 pak 5.0 v version dpak v out 0.1 ma i out 350 ma (note 3) 6.0 v v in 16 v 4.900 4.875 5.000 5.000 5.100 5.125 v output voltage d 2 pak 3.3 v version dpak v out 0.1 ma i out 350 ma (note 3) 4.5 v v in 16 v 3.234 3.217 3.300 3.300 3.366 3.383 v output voltage d 2 pak 5.0 v version dpak v out 0.1 ma i out 200 ma (note 3) 6.0 v v in 40 v 4.900 4.875 5.000 5.000 5.100 5.125 v output voltage d 2 pak 3.3 v version dpak v out 0.1 ma i out 200 ma (note 3) 4.5 v v in 40 v 3.234 3.217 3.300 3.300 3.366 3.383 v line regulation v out versus v in i out = 5 ma 6.0 v v in 28 v ? 25 5 +25 mv load regulation v out versus. i out 1.0 ma i out 350 ma (note 3) ? 40 5 +40 mv dropout voltage 5.0 v version v in ? v out i out = 200 ma (notes 3 and 4) i out = 350 ma (notes 3 and 4) ? ? 215 310 500 600 mv quiescent current i q i out 100 a t j = 25 c t j = ? 40 c to +85 c t j = 125 c 34 34 54 45 50 60 a active ground current i g (on) i out = 50 ma (note 3) i out = 350 ma (note 3) 1.8 20 3.5 40 ma power supply rejection p srr v ripple = 0.5 v pp , f = 100 hz 70 %/v output capacitor for stability 5.0 v version 3.3 v version c out esr c out esr i out = 0.1 ma to 350 ma 22 22 9 7 f f reset timing d and output r o reset switching threshold v out , r t 5.0 v version 3.3 v version 4.50 2.97 4.65 3.069 4.80 3.168 v reset output low voltage v rol r ext > 5.0k, v out > 1.0v ? 0.20 0.40 v reset output leakage current i roh v roh = 5.0 v v roh = 3.3 v ? ? 0 0 10 10 a reset charging current i d,c v d = 1.0 v 2.0 4.0 6.5 a upper timing threshold v du ? 1.2 1.3 1.4 v lower timing threshold v lu 1.24 v reset delay time 5.0 v version 3.3 v version t rd c d = 47 nf 10 10 16 16 22 24 m s reset reaction time t rr c d = 47 nf 1.5 4.0 s protection current limit i out(lim) v out = 4.5 v (5.0 v version) v out = 3.0 v (3.3 v version) 350 350 ma short circuit current limit i out(sc) v out = 0 v (note 3) 100 600 ma thermal shutdown threshold t tsd (note 5) 150 200 c 3. use pulse loading to limit power dissipation. 4. dropout voltage = (v in ? v out ), measured when the output voltage has dropped 100 mv relative to the nominal value obtained with v in = 13.5 v. 5. not tested in production. limits are guaranteed by design.
ncv8675 http://onsemi.com 4 typical characteristic curves ? 5 v version 0 2 4 6 8 10 12 0 100 200 300 output load (ma) esr ( ) figure 2. ncv8675 stability curve (5 v version) unstable region v in = 13.5 v c load 22 f stable region 0 1 2 3 4 5 6 0 1020304050 v in = 13.5 v load = 5 ma input voltage (v) output voltage (v) figure 3. ncv8675 input voltage vs. output voltage (full range) (5 v version) 0 1 2 3 4 5 6 0246810 input voltage (v) output voltage (v) figure 4. ncv8675 input voltage vs. output voltage (low voltage) (5 v version) v in = 13.5 v load = 5 ma 0 0.1 0.2 0.3 0.4 0.5 0.6 0 100 200 300 400 load current (ma) dropout voltage (v) figure 5. ncv8675 dropout voltage vs. load current (5 v version) 125 c 25 c ? 40 c 0 5 10 15 20 25 0 100 200 300 400 load current (ma) quiescent current (ma) figure 6. ncv8675 quiescent current vs. load current (full range) (5 v version) 125 c 25 c ? 40 c 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 5 10 15 20 25 load current (ma) figure 7. ncv8675 quiescent current vs. load current (light load) (5 v version) quiescent current (ma) 125 c 25 c ? 40 c v in = 13.5 v v in = 13.5 v
ncv8675 http://onsemi.com 5 typical characteristic curves ? 5 v version 0 1 2 3 4 5 6 0 1020304050 input voltage (v) figure 8. ncv8675 quiescent current vs. input voltage (5 v version) quiescent current (ma) load = 50 ma 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 ? 50 0 50 100 150 temperature ( c) figure 9. ncv8675 quiescent current vs. temperature (5 v version) quiescent current (ma) v in = 13.5 v load = 100 a 0 1 2 3 4 5 6 0 100 200 300 400 500 output load (ma) figure 10. ncv8675 output voltage vs. output load (5 v version) output voltage (v) v in =6.0 v figure 11. reset vs. output voltage (v in rising) (5 v version) figure 12. reset vs. output voltage (v in falling) (5 v version) 80 70 60 50 40 30 20 10 0 10 100 1000 10k 100k mag (db) frequency (hz) figure 13. power supply rejection ratio (5 v version) i out = 100 a v in = 13.5 v t a = 25 c c out = 22 f
ncv8675 http://onsemi.com 6 typical characteristic curves ? 5 v version 80 70 60 50 40 30 20 10 0 10 100 1000 10k 100k mag (db) frequency (hz) figure 14. power supply rejection ratio (5 v version) i out = 200 m a v in = 13.5 v t a = 25 c c out = 22 f 10 100 1000 10k 100k 80 70 60 50 40 30 20 10 0 mag (db) i out = 350 m a v in = 13.5 v t a = 25 c c out = 22 f frequency (hz) figure 15. power supply rejection ratio (5 v version) 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 ? 50 ? 25 0 25 50 75 100 125 150 output voltage (v) temperature ( c) figure 16. ncv8675 output voltage vs. temperature (5 v version) i out = 100 a i out = 200 ma i out = 350 ma v in = 13.5 v 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 0 50 100 150 200 250 300 350 400 450 500 25 c 125 c ? 40 c output voltage (v) output current (ma) figure 17. ncv8675 output voltage vs. output load (5 v version) v in = 6.0 v 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10 ? 50 ? 25 0 25 50 75 100 125 150 reset voltage (v) temperature ( c) figure 18. ncv8675 reset voltage vs. temperature (5 v version) i out = 100 a v in = 13.5 v 15 15.5 16 16.5 17 17.5 18 ? 50 0 50 100 150 temperature ( c) figure 19. ncv8675 reset delay time vs. temperature (5 v version) delay time (ms) i out = 100 a v in = 13.5 v c delay = 47 nf
ncv8675 http://onsemi.com 7 typical characteristic curves ? 5 v version temperature ( c) figure 20. ncv8675 reset threshold vs. temperature (5 v version) reset threshold (v) 4.52 4.54 4.56 4.58 4.6 4.62 4.64 4.66 4.68 4.7 ? 50 0 50 100 150 i out = 100 a v in = 13.5 v r delay = 5.0 k 620 640 660 680 700 720 740 760 780 800 820 840 860 ? 50 ? 25 0 25 50 75 100 125 150 v in = 13.5 v current limit (ma) temperature ( c) figure 21. ncv8675 current limit threshold vs. temperature (5 v version) figure 22. ncv8675 100 a ? 350 ma load transient (5 v version) c out = 22 f v in = 13.5 v output load output voltage
ncv8675 http://onsemi.com 8 typical characteristic curves ? 3.3 v version figure 23. esr stability vs. output current (3.3 v version) output current (ma) temperature ( c) 350 100 50 0 0 1.0 2.0 4.0 5.0 6.0 7.0 10 150 100 50 0 ? 50 0 10 20 30 40 50 60 70 100 k 10 k 1 k 100 10 0 10 20 40 60 70 90 100 esr ( ) quiescent current ( a) mag (db) unstable region v in = 13.5 v load = 100 a 30 50 80 i out = 100 a v in = 13.5 v t amb = 25 c c out = 22 f v in v out reset v in v out reset figure 24. input voltage vs. output voltage (3.3 v version) input voltage (v) 45 30 15 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output voltage (v) load = 5 ma figure 25. quiescent current vs. temperature (3.3 v version) figure 26. reset vs. output voltage (v in rising) (3.3 v version) figure 27. reset vs. output voltage (v in falling) (3.3 v version) figure 28. power supply rejection ratio (3.3 v version) stable region 150 200 250 300 3.0 8.0 9.0 c out = 22 f
ncv8675 http://onsemi.com 9 typical characteristic curves ? 3.3 v version output load (ma) 500 400 300 200 100 0 3.20 3.22 3.24 3.26 3.32 3.34 3.38 3.40 temperature ( c) temperature ( c) 150 100 50 0 ? 50 0 5 10 15 20 25 output voltage (v) output voltage (v) delay time (ms) 100 k 10 k 1 k 100 10 0 10 20 40 60 70 90 100 mag (db) 30 50 80 3.28 3.30 3.36 ? 40 c 125 c 25 c v in = 13.5 v i out = 350 ma v in = 13.5 v t amb = 25 c c out = 22 f 150 100 50 0 ? 50 3.20 3.22 3.24 3.26 3.32 3.34 3.38 3.28 3.30 3.36 v in = 13.5 v load = 5 ma v in = 13.5 v load = 100 a 3.40 figure 29. power supply rejection ratio (3.3 v version) 100 k 10 k 1 k 100 10 0 10 20 40 60 70 90 100 mag (db) 30 50 80 i out = 250 ma v in = 13.5 v t amb = 25 c c out = 22 f figure 30. power supply rejection ratio (3.3 v version) figure 31. output voltage vs. output load (3.3 v version) figure 32. output voltage vs. temperature (3.3 v version) figure 33. reset delay time vs. temperature (3.3 v version)
ncv8675 http://onsemi.com 10 figure 34. application circuits 100 nf 47 nf gnd d 2 5 3 4 1 ro ncv8675 c d c in c out 22 f r ext 5.0 k v out v ro v in i out i ro i d i g v out v in circuit description the ncv8675 is an integrated low dropout regulator that provides 5.0 v 350 ma, or 3.3 v 350 ma protected output and a signal for power on reset. the regulation is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. the output current capability is 350 ma, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. the delay time for the reset output is adjustable by selection of the timing capacitor. see figure 34, test circuit, for circuit element nomenclature illustration. regulator the error amplifier compares the reference voltage to a sample of the output voltage (v out ) and drives the base of a pnp series pass transistor by a buffer. the reference is a bandgap design to give it a temperature ? stable output. saturation control of the pnp is a function of the load current and input voltage. oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. regulator stability considerations the input capacitor (c in ) is necessary to stabilize the input impedance to avoid voltage line influences. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacit or value and type should be based on cost, availability, size and temperature constraints. ceramic, tantalum, or electrolytic capacitors of 22 f, or greater, are stable with very low esr values. refer to figure 2 for specific esr ratings. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the capacitance and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c out shown in figure 13, test circuit, should work for most applications; however, it is not necessarily the optimized solution. reset output the reset output is used as the power on indicator to the microcontroller. this signal indicates when the output voltage is suitable for reliable operation of the controller. it pulls low when the output is not considered to be ready. ro is pulled up to v out by an external resistor, typically 5.0 k in value. the input and output conditions that control the reset output and the relative timing are illustrated in figure 35, reset t iming. output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. the delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0 v to the upper timing threshold voltage v du of 1.3 v. the char ging current for this is i d of 4 a and d pin voltage in steady state is typically 2.4 v. by using typical ic parameters with a 47 nf capacitor on the d pin, the following time delay is derived: t rd c d *v du i d t rd 47 nf * (1.3 v) 4 a 15.3 ms other time delays can be obtained by changing the c d capacitor value. the delay time can be reduced by decreasing the capacitance of c d . using the formula above, delay can be reduced as desired. leaving the delay pin open is not desirable as it can result in unwanted signals being coupled onto the pin.
ncv8675 http://onsemi.com 11 figure 35. reset timing v i v q v d v ro reset delay time reset reaction time power ? on ? re- set thermal shutdown voltage dip at input undervoltage secondary spike overload at output < reset reaction time t t t t v q,rt upper timing threshold v du lower timing threshold v dl dv d dt reset charge current c d
ncv8675 http://onsemi.com 12 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 36) is: p d(max) [v in(max) v out(min) ]i out(max) (1) v i(max) i q where v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i out i in figure 36. single output regulator with key performance parameters labeled v in v out } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where r jc is the junction ? to ? case thermal resistance, r cs is the case ? to ? heatsink thermal resistance, r sa is the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heatsink data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d. copper area (mm 2 ) figure 37. ja vs. copper spreader area thermal resistance junction ? to ? air ( c/w) r(t), ( c/w) pulse time (sec) figure 38. ncv8675 @ pcb cu area 100 mm 2 pcb cu thk 1 oz 20 40 60 100 120 0 100 200 300 400 500 600 700 800 900 d 2 pak 1 oz d 2 pak 2 oz 0.1 1 10 100 0.000001 0.0001 0.01 1 100 d 2 pak dpak dpak 1 oz dpak 2 oz 80 single pulse
ncv8675 http://onsemi.com 13 emc ? characteristics: conducted susceptibility all emc ? characteristics are based on limited samples and no part of production test according to 47a/658/cd iec62132 ? 4 (direct power injection). test conditions supply voltage v in = 12 v temperature t a = 23 c + ? 5 c load r l = 100 direct power injection 33d bm (note 1) forward power cw for global pin (note 2) 17 dbm (note 1) forward power cw for local pin (note 3) acceptance criteria amplitude dev. max 4% of output voltage reset outputs remain in correct state + ? 1 v 1. dbm means db milli ? watts, p (dbm) = 10 log (p (mw) ) 2. a global pin carries a signal or power which enters or leaves the application board 3. a local pin carries a signal or power which does not leave the application board. it remains on the application board as a signal between two components figure 39. test circuit c6 47 nf x8 d_hf x7 d_dc x6 vout_hf c4 47 nf x5 vout_dc c5 22 f ferrite l3 ferrite l1 ferrite l2 ferrite l4 x4 ro_hf x3 ro_dc x2 vin_hf x1 vin_dc r1 4.99k vout 1 2 5 4 3 ro d gnd ncv8675 u1 c2 15 f c1 100 nf v out v in v out
ncv8675 http://onsemi.com 14 40 30 20 10 0 v in pass 33 dbm (dbm) frequency (mhz) figure 40. typical v in pin susceptibility 1 10 100 1000 frequency (mhz) figure 41. typical v out pin susceptibility 1 10 100 100 0 (dbm) 40 30 20 10 0 v out pass 33 dbm 25 20 15 10 5 0 (dbm) frequency (mhz) figure 42. typical r o pin susceptibility 1 10 100 1000 r o pass 17 dbm (dbm) frequency (mhz) figure 43. typical delay pin susceptibility 25 20 15 10 5 0 1 10 100 100 0 delay pass 17 dbm ordering information device output voltage package shipping ? ncv8675ds50g 5.0 v d 2 pak (pb ? free) 50 units / rail ncv8675ds50r4g 800 / tape & reel NCV8675DT50RKG dpak (pb ? free) 2500 / tape & reel ncv8675ds33g 3.3 v d 2 pak (pb ? free) 50 units / rail ncv8675ds33r4g 800 / tape & reel ncv8675dt33rkg dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8675 http://onsemi.com 15 package dimensions dpak ? 5, center lead crop case 175aa ? 01 issue a *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1 mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint*
ncv8675 http://onsemi.com 16 package dimensions 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 5 ? lead d 2 pak scale 3:1 mm inches d 2 pak ? 5 case 936a ? 02 issue c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8675/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of NCV8675DT50RKG

	To Download NCV8675DT50RKG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .